I always quite fancied the idea of having a Virtual Machine in here, a bit like the old Chip 8. I do like the CP1610 and it's fun to code for, but the defects described elsewhere in respect to the RAM system spoil it really.
So I came up with this design. It's a RISC system with a 20 bit instruction word. Every instructional is conditional on simple status bits (Carry Out, Sign and Zero). It is designed for 8 bit usage without much memory - what I've done is shifted the memory map slightly so the display is now at $40 (rather than $00), so the last 64 bytes of RAM at $C0-$FF are now at $00-$3F in the virtual machine and become R0-R63, rather like on an 8048 Microcontroller. The sound byte shifts from $96 to $D6 - every address goes $40 forward.
This is of course in the RISC interpreter - I'm not cheating by changing the actual target machine - to keep me honest it has to run as if it ran on the real machine.
There are, arguably, 8 instructions. The four data instructions, add, and, xor and mov which have two operands - the left one can either be a direct register (e.g. r2) or an indirect offset (e.g. 4(r3)). The right one can either be a similar register address, or it can be a 7 bit constant which is sign extended to 8 bits (I don't have many bits to work with !)
There are 2 branch instructions, branch and branch link which are jump and subroutine call respectively, they take a 15 bit operand (every instruction is 2 decles so is on an even address) which is relative, which makes all the code relative (there is no option to do indirect jumps)
The two left are fiddles. branch link 0 , e.g. a subroutine call to the next address is used for return, and branch 0, e.g. branch to the next address is used to access some basic system functions (e.g. a random number generator). Both of these are effectively useless (you could actually have branch-link 0 in some rare cases) so are coopted to do other things.
This gives me two options for producing a hardware version. My calculations suggest a typical Arduino Uno can actually keep up with generating the video and emulating a CP1610 in real time on this machine, remarkably. Alternatively the hardware version could just dump the CP1610 and use a 'C' based RISC interpreter.
Haven't really decided yet :)
Anyway, this is the specification document (pdf)
Next task is to write an assembler for it.
Because almost every instruction is basically the same, this isn't too difficult.